1. Field of the Invention
The present invention relates to a digital arithmetic integrated circuit (or a digital signal processor), and more specifically to a digital arithmetic integrated circuit provided with a circuit section for executing arithmetic operation at high speed and at high precision.
2. Description of the Prior Art
With the recent advance of LSIs and signal processing techniques, the digitalization technique of data communications terminals has progressed rapidly. However, in the field of portable data communications apparatus, in particular, a further advance of the technique is still required. For instance, there exist various desires such as solution of the insufficient circuit capacity, reduction of the noise, improvement of the privacy or secrecy, shortening of the speech waiting time, etc. with the spread of the portable data communications apparatus. Accordingly, in the recent portable data communications apparatus, a digital communication processing LSI or a digital signal processor (referred to as DSP, hereinafter) has become indispensable, and a key of the spread of the portable data communications apparatus is dependent upon the higher precision and the higher operation speed of the DSP.
Here, in the digital signal processing by use of the DSP, since the major part of the processing time is occupied by product-addition operations, that is, by accumulative additions of the multiplication results, a great problem with respect to the development of the DSP is how to execute the product-addition operations at a high speed and further at a high arithmetic precision.
On the other hand, when the arithmetic operation speed thereof is improved by increasing the clock frequency, current caused by charge and discharge within the LSI in unit time increases, thus causing an increase of the power consumption thereof. To overcome this problem, therefore, the operation speed thereof has been so far improved by parallel processing (i.e., pipeline processing). In this pipeline processing method, a plurality of processings are executed simultaneously in parallel to each other, so that it is possible to increase the throughput in a unit time without increasing the clock frequency.
A conventional DSP so far adopted will be described hereinbelow with reference to FIG. 7. In the drawing, the DSP is roughly composed of an arithmetic data storing memory 101 for storing arithmetic data (referred to as data, simply), two arithmetic operand registers 102 each for storing an arithmetic operand, a parallel multiplier 103, an arithmetic logical unit 104, and an arithmetic result register 105 for storing operation results obtained by the parallel multiplier 103 and the arithmetic logical unit 104. Here, the parallel multipliers 103 and the arithmetic logical unit 104 are sometime constructed as a same single unit, which is referred to as an accumulative adder 106. Further, the above-mentioned registers 102 and 105 are constructed by a latch circuit or a flip-flop circuit, respectively. Further, in FIG. 7, the numbers of bits of the respective data are also shown, by way of example.
Further, the above-mentioned construction is the same in both the single precision DSP and the double precision DSP. In the case of the double precision DSP, however, since the number of bits of the arithmetic data to be processed is larger than that of the single precision DSP, the capacities of the respective units, the signal lines for data transmission, etc. become inevitably large,
Conventionally, when the high speed processing is considered as being important, the single precision DSP is used to execute the single precision operation in fixed-point method. When the operation precision is considered as being important, on the other hand, since a large operational error is inevitably produced in the single precision operation, the operational error must be always taken into account whenever programs are being prepared. However, in the data processing, there exist some cases where the high precision operation is rather essential.
In the conventional single precision DSP for processing data at high precision, the following method has been so far adopted: The ordinary data processing which does not required a high precision is executed at high speed by the single precision operation, and only the data processing which requires a high precision is executed at double precision by use of the single precision DSP.
However, when the above-mentioned method such that the double precision operation is executed by use of the single precision DSP is adopted, the following problems arise: For instance, when the double precision operation is executed by use of the single precision DSP constructed as shown in FIG. 7, the procedure of four cycles as shown in FIG. 8 is required. In more detail, when high-order 16-bit data are denoted by XH and YH and low-order 16-bit data are denoted by XL and YL, respectively, four cycles are necessary to execute the multiplication of (XH+XL)xc3x97(YH+YL). In addition, since the reading of the arithmetic data from the memories, the digit position arrangement of the multiplication results, the addition processing for obtaining the final results, etc. are required, a series of about 6 to 8 processing cycles is needed, thus resulting in a long processing time.
Further, in the above-mentioned example, although the multiplication of 16 bit data has been explained, when the double precision operation is executed for a word length longer than the above (16 bits) by use of the single precision DSP, the processing cycles inevitably increase markedly.
Consequently, when the double precision operations are executed frequently by use of the single precision DSP, there exists a problem in that the double precision operation takes a long time, so that the high speed operation is inevitably limited to some extent.
Therefore, in the case where processing including many high precision operations is executed, the double precision DSP for enabling a high speed processing is often used, as compared with when the double precision operation is executed by the single precision DSP as described above. When the double precision DSP is used, the memory capacity, the signal line capacity, etc. are extended within the DSP, as compared with the case of the single precision DSP. In addition, the circuit scale of external peripheral circuits of the DSP are extended in accordance with the double precision specifications, in comparison with the single precision DSP. In particular, the total element including the DSP and the peripheral circuits (other than the DSP) are large-sized. In addition, the power consumed by the peripheral circuits also increases, as compared with that of the total element including the single precision DSP and the peripheral circuits.
When the double precision DSP is used, since the number of bits of the arithmetic data can be extended, high precision operation can be executed. However, when the single precision operation (which do not require a high precision) is executed by use of the double precision DSP, since the high- or lower-order bits of the arithmetic data must be changed to xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, the double precision specifications of not only the double precision DSP body but also the peripheral circuits are wasted. Further, the power consumption of the peripheral circuits are also wasteful.
As described above, in the arithmetic data processing, there are two cases where the high precision operation is essential and where high speed operation is required rather than the operation precision. In the conventional DSP, however, when the single precision operation is executed by the processor constructed by the double-precision DSP, there exist problems in that the double precision specifications of the DSP and the peripheral circuits are wasted and further the power consumption thereof is also wasteful.
With these problems in mind, therefore, it is the object of the present invention to provide a digital arithmetic integrated circuit or a digital signal processor which can execute high precision operation at high speed.
To achieve the above-mentioned object, the present invention provides a digital arithmetic integrated circuit, comprising: an arithmetic data storing memory for storing arithmetic data and for outputting, in one instruction cycle, first and second arithmetic data strings each composed of a plurality of bits, the first arithmetic data string being composed of m-bits of at least a predetermined unit word length and the second arithmetic data string being composed of (mxc3x97n)-bits n-times longer than that m-bits of the unit word length of the first arithmetic data string; two arithmetic operand storing registers for storing the first and second arithmetic data strings outputted by said arithmetic data storing memory, respectively; an arithmetic logical unit for executing arithmetic operation on the basis of the two operands outputted by said arithmetic operand storing registers in one instruction cycle; and an arithmetic result storing register for storing the arithmetic results outputted by said arithmetic logical unit.